(1) Technical Field
This invention relates to electronic radio frequency (RF) circuits, and more particularly to programmable multi-state RF phase shifter circuits.
(2) Background
Electronic phase shifter circuits are used to change the transmission phase angle of a signal, and are commonly used to phase shift radio frequency (RF) signals. It is often necessary to change the phase of RF signals for applications such as in-phase discriminators, beam forming networks, power dividers, linearization of power amplifiers, and phased array antennas, to name a few. Modern phase shifter circuits may be digitally controlled and thus provide a discrete set of phase states that are selected by a digital control word.
FIG. 1 is a block diagram of a conventional 3-bit (8 state) binary-weighted, series connected phase shifter 100. The illustrated phase shifter 100 includes three series-connected phase shift cells 102-1 to 102-3, each including a respective inductor L1-L3 and capacitor C1-C3, and respective pairs of single-pole, double-throw (SPDT) switches S1a-S1b, S2a-S2b, S3a-S3b (generically, Sna).
The switch pairs Sna-Snb in each phase shift cell 102-1 to 102-3 provide input/output symmetry and are concurrently switched to define mutually exclusive signal paths that allow either the associated inductor L1-L3 or the associated capacitor C1-C3 (but not both at the same time) to be placed in-circuit in response to an applied signal from a control circuit (not shown, but conventional). The switches Sna are typically implemented with field effect transistors (FETs), particularly MOSFETs. Because of the SPDT function of the switches Sna, and since FETs are inherently single-pole, single-throw (SPST) devices, typically at least two FETs (or FET stacks, as discussed below) are required to implement each switch Sna. Accordingly, for the phase shifter 100 of FIG. 1, at least 12 FETs are required (although only 6 FETs will be in series between RF1 and RF2 at any particular time).
The values of the inductors L1-L3 and capacitors C1-C3 may be the same but will typically differ somewhat. For example, the three phase shift cells 102-1 to 102-3 may be configured to respectively provide 1.4°, 2.8°, and 1.4° of phase shift (i.e., L1=L3 and C1=C3). For such a configuration, example values for the inductors L1-L3 and capacitors C1-C3 are set forth in TABLE 1.
TABLE 1Example Component ValuesL1, L30.085nHC1, C349.7pFL20.17nHC224.8pF
With three series-connected phase shift cells 102-1 to 102-3, the combinations of inductors and capacitors shown in TABLE 2 can be switched into circuit to shift the phase of an RF signal applied to either port, RF1 or RF2. Accordingly, phase shifter 100 when configured with the values in TABLE 1 can provide phase shifts of 0°, 1.4°, 2.8°, 4.2°, and 5.6° (the number of distinct phase shift states is less than 23 because the phase shift cells 102-1 and 102-3 provide the same amount of phase shift). Note that the illustrated mapping of control bits to in-circuit elements is arbitrary and that other mappings are possible. For example, phase shifter 100 can provide phase shifts of −1.4°, 0°, 1.4°, 2.8°, and 4.2° if State 2 in TABLE 2 is used as the reference state (that is, the phase shift cell 102-3 is set to +1.4° in the reference state); the same result may be achieved by selecting State 5 as the reference state.
TABLE 2StateControl BitsIn-Circuit ElementsPhase Shift1000C1-C2-C30°  2001C1-C2-L31.4°3010C1-L2-C32.8°4011C1-L2-L34.2°5100L1-C2-C31.4°6101L1-C2-L32.8°7110L1-L2-C34.2°8111L1-L2-L35.6°
Series-cell phase shifter architectures suffer from excessive insertion loss (IL) due to the cumulative IL of each switch Sna of the serially-connected phase shifter cells. In the embodiment illustrated in FIG. 1, there are always 6 series switches (FETs) in-circuit in the 3-bit phase shifter 100. The IL problem is exacerbated when additional phase shifter cells are added, since each additional cell adds another pair of series switches (FETs). Further, as the total resistance of the series connected FETs increases, the return loss also becomes worse (i.e., becomes a smaller positive value).
Accordingly, there is a need for a multi-state phase shifter circuit having both low insertion loss and good return loss. The present invention addresses these needs.